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| 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information The SST26WF032 Serial Quad I/OTM (SQITM) flash device utilizes a 4-bit multiplexed I/O serial interface to boost performance while maintaining the compact form factor of standard serial flash devices. Operating at frequencies reaching 80 MHz, the SST26WF032 enables minimum latency execute-inplace (XIP) capability without the need for code shadowing on an SRAM. The device's high performance and small footprint make it the ideal choice for mobile handsets, Bluetooth headsets, optical disk drives, GPS applications and other portable electronic products. Further benefits are achieved with SST's proprietary, high-performance CMOS SuperFlash(R) technology, which significantly improves performance and reliability, and lowers power consumption for high bandwidth, compact designs. Features: * Single Voltage Read and Write Operations - 1.65-1.95V * Flexible Erase Capability - Uniform 4 KByte sectors - Four 8 KByte top and bottom parameter overlay blocks - Two 32 KByte top and bottom overlay blocks - Uniform 64 KByte overlay blocks - SST26WF032 - 62 blocks * Serial Interface Architecture - Nibble-wide multiplexed I/O's with SPI-like serial command structure - Mode 0 and Mode 3 - Single-bit, SPI backwards compatible - Read, High-Speed Read, and JEDEC ID Read * Write-Suspend - Suspend Program or Erase operation to access another block/sector * High Speed Clock Frequency - 80 MHz - 320 Mbit/s sustained data rate * Software Reset (RST) mode * Software Write Protection - Individual Block-Locking - 64 KByte blocks, two 32 KByte blocks, and eight 8 KByte parameter blocks - Write Lock, Read Lock, and Lockdown options * Burst Modes - Continuous linear burst - 8/16/32/64 Byte linear burst with wrap-around * Superior Reliability - Endurance: 100,000 Cycles - Greater than 100 years Data Retention * Security ID - One-Time Programmable (OTP) 256 bit, Secure ID - 64 bit unique, factory pre-programmed identifier - 192 bit user-programmable * Low Power Consumption: - Active Read current: 12 mA (typical @ 80 MHz) - Standby Current: 8 A (typical) * Temperature Range - Industrial: -40C to +85C * Fast Erase and Byte-Program: - Chip-Erase time: 35 ms (typical) - Sector-/Block-Erase time: 18 ms (typical) * Packages Available - 8-contact WSON (6mm x 5mm) - 8-lead SOIC (200 mil) * Page-Program - 256 Bytes per page - Fast Page Program time in 1 ms (typical) * All devices are RoHS compliant * End-of-Write Detection - Software polling the BUSY bit in status register (c)2010 Silicon Storage Technology, Inc. www.sst.com S71409-01-000 01/10 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Product Description The Serial Quad I/OTM (SQITM) family of flash-memory devices features a 4-bit, multiplexed I/O interface that allows for low-power, high-performance operation in a low pin-count package. System designs using SQI flash devices occupy less board space and ultimately lower system costs. All members of the 26 Series, SQI family are manufactured with SST proprietary, high-performance CMOS SuperFlash(R) technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST26WF032 significantly improves performance and reliability, while lowering power consumption. This device writes (Program or Erase) with a single power supply of 1.65-1.95V. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. SST26WF032 is offered in both 8-contact WSON (6 mm x 5 mm), and 8-lead SOIC (200 mil) packages. See Figure 2 for pin assignments. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 2 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Block Diagram Address Buffers and Latches X - Decoder SuperFlash Memory Y - Decoder Control Logic Page Buffer, I/O Buffers and Data Latches Serial Interface CE# Figure 1: Functional Block Diagram SCK SIO [3:0] 1409 B1.0 (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 3 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Pin Description CE# SO/SIO1 SIO2 VSS 1 2 8 7 VDD SIO3 SCK SI/SIO0 CE# SO/SIO1 SIO2 VSS 1 8 VDD SIO3 SCK SI/SIO0 2 7 Top View 3 4 6 5 3 Top View 6 4 5 1409 08-soic S2A P1.0 1409 08-wson QA P1.0 8-Lead SOIC 8-Contact WSON Figure 2: Pin Description for 8-lead SOIC and 8-contact WSON Table 1: Pin Description Symbol SCK Pin Name Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device or data out of the device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on the falling edge of the serial clock. The EQIO command instruction configures these pins for Quad I/O mode. To transfer commands, addresses or data serially into the device. Inputs are latched on the rising edge of the serial clock. SI is the default state after a power on reset. SIO[3:0] Serial Data Input/Output SI Serial Data Input for SPI mode SO CE# Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling for SPI mode edge of the serial clock. SO is the default state after a power on reset. Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence; or in the case of Write operations, for the command/data input sequence. To provide power supply voltage: 1.65-1.95V T1.0 1409 VDD VSS Power Supply Ground (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 4 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Memory Organization The SST26WF032 SQI memory array is organized in uniform, 4 KByte erasable sectors with erasable overlay blocks: eight 8 KByte parameter blocks, two 32 KByte blocks, and sixty-two 64 KByte blocks. See Figure 3. Top of Memory Block 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte 64 KByte 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks 4 KByte 4 KByte 4 KByte 4 KByte 64 KByte 32 KByte 8 KByte 8 KByte 8 KByte 8 KByte Bottom of Memory Block 1409 F41.0 Figure 3: Memory Map (c)2010 Silicon Storage Technology, Inc. ... 64 KByte ... S71409-01-000 01/10 5 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Device Operation The SST26WF032 supports both Serial Peripheral Interface (SPI) bus protocol and the new 4-bit multiplexed Serial Quad I/O (SQI) bus protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the device's initial state after a power-on reset is SPI bus protocol supporting only Read, High Speed Read, and JEDEC-ID Read instructions. A command instruction configures the device to Serial Quad I/O bus protocol. The dataflow in this bus protocol is controlled with four multiplexed I/O signals, a chip enable (CE#), and serial clock (SCK). SQI Flash Memory protocol supports both Mode 0 (0,0) and Mode 3 (1,1) bus operations. The difference between the two modes, as shown in Figures 4 and 5, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data I/O (SIO[3:0]) is sampled at the rising edge of the SCK clock signal for input, and driven after the falling edge of the SCK clock signal for output. The traditional SPI protocol uses separate input (SI) and output (SO) data signals as shown in Figure 4. The SST26WF032 uses four multiplexed signals, SIO[3:0], for both data in and data out, as shown in Figure 5. This quadruples the traditional bus transfer speed at the same clock frequency, without the need for more pins on the package. CE# MODE 3 MODE 3 MODE 0 SCK SI SO MODE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 1409 F03.0 HIGH IMPEDANCE Figure 4: SPI Protocol (Traditional 25 Serial SPI Device) CE# MODE 3 MODE 3 CLK MODE 0 MODE 0 SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 MSB L0 H1 L1 H2 L2 H3 L3 X = Don't Care or High Impediance 1409 F04.1 Figure 5: SQI Serial Quad I/O Protocol (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 6 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Device Protection The SST26WF032 has a Block-Protection register which provides a software mechanism to write-lock the array and write-lock, and/or read-lock, the parameter blocks. The Block-Protection Register is 80 bits wide per device: two bits each for the eight 8 KByte parameter blocks (write-lock and read-lock), and one bit each for the remaining 32 KByte and 64 KByte overlay blocks (write-lock). See Table 8 for address range protected per register bit. Each bit in the Block-Protection Register can be written to a `1' (protected) or `0' (unprotected). For the parameter blocks, the most significant bit is for read-lock, and the least significant bit is for write-lock. Readlocking the parameter blocks provides additional security for sensitive data after retrieval (e.g., after initial boot). If a block is read-locked all reads to the block return data 00H. All blocks are write-locked and readunlocked after power-up. The Write Block Locking Register command is a two cycle command requiring Write-Enable (WREN) to be executed prior to the Write Block-Protection Register command. Top of Memory Block 8 KByte Read Lock Write Lock 8 KByte 8 KByte 8 KByte 32 KByte 64 KByte Write Lock 64 KByte 64 KByte 32 KByte 8 KByte Read Lock Write Lock 8 KByte 8 KByte 8 KByte Bottom of Memory Block ... 1409 F40.0 Figure 6: Block Locking Memory Map (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 7 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Write-Protection Lock-Down To prevent changes, the Block-Protection register can be set to Write-Protection Lock-Down using the Lock Down Block Protection Register (LPBR) command. Once the Write-Protection Lock-Down is enabled, the Block-Protection register can not be changed. To avoid inadvertent lock down, the WREN command must be executed prior to the LBPR command. To reset Write-Protection Lock-Down, power cycle the device. The Write-Protection Lock-Down status may be read from the Status register. Security ID SST26WF032 offers a 256-bit Security ID (Sec ID) feature. The Security ID space is divided into two parts - one factory-programmed, 64-bit segment and one user-programmable 192-bit segment. The factory-programmed segment is programmed at SST with a unique number and cannot be changed. The user-programmable segment is left unprogrammed for the customer to program as desired. Use the SecID Program command to program the Security ID using the address shown in Table 7. Once programmed, the Security ID can be locked using the Lockout Sec ID command. This prevents any future write to the Security ID. The factory-programmed portion of the Security ID can't be programmed by the user; neither factorprogrammed nor user-programmable areas can be erased. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 8 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Status Register The Status register is a read-only register that provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and whether an erase or program operation is suspended. During an internal Erase or Program operation, the Status register may be read to determine the completion of an operation in progress. Table 2 describes the function of each bit in the Status register. Table 2: Status Register Bit 0 1 Name RES WEL Function Reserved for future use Write-Enable Latch status 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Write Suspend-Erase status 1 = Erase suspended 0 = Erase is not suspended Write Suspend-Program status 1 = Program suspended 0 = Program is not suspended Write Protection Lock-Down status 1 = Write Protection Lock-Down enabled 0 = Write Protection Lock-Down disabled Security ID status 1 = Security ID space locked 0 = Security ID space not locked Reserved for future use Write operation status 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress Default at Power-up 0 0 2 WSE 0 3 WSP 0 4 WPLD 0 5 SEC1 01 6 7 RES BUSY 0 0 T2.0 1409 1. The Security ID status will always be `1' at power-up after a successful execution of the Lockout Sec ID instruction, otherwise default at power-up is `0'. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 9 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Write-Enable Latch (WEL) The Write-Enable Latch (WEL) bit indicates the status of the internal memory's Write-Enable Latch. If the WEL bit is set to `1', the device is write enabled. If the bit is set to `0' (reset), the device is not write enabled and does not accept any memory Program or Erase, Protection Register Write, or Lock-Down commands. The Write-Enable Latch bit is automatically reset under the following conditions: * * * * * * * * * * * * Power-up Reset Write-Disable (WRDI) instruction completion Page-Program instruction completion Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Block-Protection register instruction Lock-Down Block-Protection register instruction Program Security ID instruction completion Lockout Security ID instruction completion Write-Suspend instruction Write Suspend Erase Status (WSE) The Write Suspend-Erase Status (WSE) indicates when an Erase operation has been suspended. The WSE bit is `1' after the host issues a suspend command during an Erase operation. Once the suspended Erase resumes, the WSE bit is reset to `0.' Write Suspend Program Status (WSP) The Write Suspend-Program Status (WSP) bit indicates when a Program operation has been suspended. The WSP is `1' after the host issues a suspend command during the Program operation. Once the suspended Program resumes, the WSP bit is reset to `0.' Write Protection Lockdown Status (WPLD) The Write Protection-Lockdown Status (WPLD) bit indicates when the Block Protection register is locked-down to prevent changes to the protection settings. The WPLD is `1' after the host issues a Lock-Down Block Protection command. After a power cycle, the WPLD bit is reset to `0.' Security ID Status (SEC) The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write command. The SEC is `1' after the host issues a Lockout SID command. Once the host issues a Lockout SID command, the SEC bit can never be reset to `0.' Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. If the BUSY bit is `1', the device is busy with an internal Erase or Program operation. If the bit is `0', no Erase or Program operation is in progress. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 10 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Instructions Instructions are used to read, write (erase and program), and configure the SST26WF032. The instruction bus cycles are two nibbles each for commands (Op Code), data, and addresses. Prior to executing any write instructions, the Write-Enable (WREN) instruction must be executed. The complete list of the instructions is provided in Table 3. All instructions are synchronized off a high to low transition of CE#. Inputs are accepted on the rising edge of SCK starting with the most significant nibble. CE# must be driven low before an instruction is entered and must be driven high after the last nibble of the instruction has been input (except for read instructions). Any low-to-high transition on CE# before receiving the last nibble of an instruction bus cycle, will terminate the instruction being entered and return the device to the standby mode. Table 3: Device Operation Instructions for SST26WF032 Instruction NOP RSTEN RST3 EQIO RSTQIO4 Read5 Description No Operation Reset Enable Reset Memory Enable Quad I/O Reset Quad I/O Read Memory Command Cycle1 00H 66H 99H 38H FFH 03H 0BH C0H 0CH 9FH AFH 20H D8H Address Cycle(s)2 0 0 0 0 0 3 3 0 3 0 0 3 3 Dummy Cycle(s) 0 0 0 0 0 0 2 0 2 0 0 0 0 Data Cycle(s) 0 0 0 0 0 1 to 1 to 1 n to 3 to 3 to 0 0 25 MHz 80 MHz Maximum Frequency High-Speed Read5 Read Memory at Higher Speed Set Burst6 Read Burst JEDEC-ID 5,7 Quad J-ID7 Sector Erase8 Set Burst Length nB Burst with Wrap JEDEC-ID Read Quad I/O J-ID Read Erase 4 KBytes of Memory Array Erase 64, 32 or 8 KBytes of Memory Array Erase Full Array Program 1 to 256 Data Bytes Suspends Program/ Erase Resumes Program/ Erase Read Security ID Program User Security ID area Lockout Security ID Programming Read Status Register Write Enable Block Erase9 Chip Erase Page Program Write Suspend Write Resume Read SID Program SID10 C7H 02H B0H 30H 88H A5H 85H 05H 06H 0 3 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 1 to 256 0 0 1 to 32 1 to 24 0 1 to 0 80 MHz Lockout SID10 RDSR11 WREN (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 11 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Table 3: Device Operation Instructions for SST26WF032 Instruction WRDI RBPR12 WBPR10,12 LBPR10 Description Write Disable Read Block Protection Register Write Block Protection Register Lock Down Block Protection Register Command Cycle1 04H 72H 42H 8DH Address Cycle(s)2 0 0 0 0 Dummy Cycle(s) 0 0 0 0 Data Cycle(s) 0 1 to m/4 1 to m/4 0 T3.0 1409 Maximum Frequency 80 MHz 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. One BUS cycle is two clock periods (command, access, or data). Address bits above the most significant bit of each density can be VIL or VIH. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode. After a power cycle, Read, High-Speed Read, and JEDEC-ID Read instructions input and output cycles are SPI bus protocol. Burst length- n = 8 Bytes: Data(00H); n = 16 Bytes: Data(01H); n = 32 Bytes: Data(02H); n = 64 Bytes: Data(03H). The Quad J-ID read wraps the three Quad J-ID Bytes of data until terminated by a low-to-high transition on CE# Sector Addresses: Use AMS - A12, remaining address are don't care, but must be set to VIL or VIH. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS A15 for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don't care, but must be set to VIL or VIH. Requires a prior WREN command. The Read-Status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#. Data is written/read from MSB to LSB. MSB = 79 for SST26WF032. No Operation (NOP) The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 12 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Reset-Enable (RSTEN) and Reset (RST) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the SST26WF032, the host drives CE# low, sends the Reset-Enable command (66H), and drives CE# high. Next, the host drives CE# low again, sends the Reset command (99H), and drives CE# high, see Figure 7. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. A successful command execution will reset the burst length to 8 Bytes and all the bits in the Status register to their default states, except for bit 4 (WPLD) and bit 5 (SEC). A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more latency time than recovery from other operations. TCPH CE# MODE 3 MODE 3 MODE 3 CLK MODE 0 MODE 0 MODE 0 SIO(3:0) C1 C0 C3 C2 1409 F05.0 Note: C[1:0] = 66H; C[3:2] = 99H Figure 7: Reset sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 13 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Read (25 MHz) The Read instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 25 MHz. This command is not supported in SQI bus protocol. The device outputs the data starting from the specified address location, then continuously streams the data output through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically return to the beginning (wrap-around) of the address space. Initiate the Read instruction by executing an 8-bit command, 03H, followed by address bits A23:A0. CE# must remain active low for the duration of the Read cycle. SIO2 and SIO3 must be driven VIH for the duration of the Read cycle. See Figure 8 for Read Sequence. CE# MODE 3 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SCK MODE 0 SI MSB SO 03 ADD. MSB HIGH IMPEDANCE ADD. ADD. N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT 1409 F29.0 Note: SIO2 and SIO3 must be driven VIH Figure 8: Read Sequence (SPI) Enable Quad I/O (EQIO) The Enable Quad I/O (EQIO) instruction, 38H, enables the flash device for SQI bus operation. upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or a "Reset Quad I/O instruction" is executed. See Figure 9. CE# MODE 3 0 1 2 3 4 5 6 7 SCK SIO0 SIO[3:1] MODE 0 38 1409 F43.0 Figure 9: Enable Quad I/O Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 14 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Reset Quad I/O (RSTQIO) The Reset Quad I/O instruction, FFH, resets the device to 1-bit SPI protocol operation. To execute a Reset Quad I/O operation, the host drives CE# low, sends the Reset Quad I/O command cycle (FFH) then, drives CE# high. The device accepts either SPI (8 clocks) or SQI (2 clocks) command cycles. For SPI, SIO[3:1] are don't care for this command, but should be driven to VIH or VIL. High-Speed Read (80 MHz) The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On power-up, the device is set to use SPI. Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. SIO2 and SIO3 must be driven VIH for the duration of the Read cycle. See Figure 10 for the High-Speed Read sequence for SPI bus protocol. CE# MODE 3 SCK MODE 0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI/SIO0 0B ADD. HIGH IMPEDANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT 1409 F31.0 SO/SIO1 Note: SIO2 and SIO3 must be driven VIH Figure 10:High-Speed Read Sequence (SPI) In SQI protocol, the host drives CE# low then send the Read command cycle command, 0BH, followed by three address cycles and two dummy cycles. Each cycle is two nibbles (clocks) long, most significant nibble first. After the dummy cycles, the 1.8V Serial Quad I/O (SQI) Flash Memory outputs data on the falling edge of the SCK signal starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to address location 000000H. During this operation, blocks that are Read-locked will output data 00H. CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 SCK MODE 0 MSN LSN SIO(3:0) C0 C1 A5 A4 A3 A2 A1 A0 X X X X H0 L0 H8 L8 H9 L9 Command Address Dummy Data Byte 0 Data Byte 8 Data Byte 9 1409 F44.1 Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble Figure 11:High-Speed Read and Read Burst Sequence (SQI) (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 15 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Set Burst The Set Burst command specifies the number of bytes to be output during a Read Burst command before the device wraps around. To set the burst length the host drives CE# low, sends the Set Burst command cycle (C0H) and one data cycle, then drives CE# high. A cycle is two nibbles, or two clocks, long, most significant nibble first. After power-up or reset, the burst length is set to eight Bytes (00H). See Table 4 for burst length data and Figure 12 for the sequence. Table 4: Burst Length Data Burst Length 8 Bytes 16 Bytes 32 Bytes 64 Bytes High Nibble (H0) 0h 0h 0h 0h Low Nibble (L0) 0h 1h 2h 3h T4.0 1409 CE# MODE 3 0 1 2 3 SCK SIO(3:0) MODE 0 C1 C0 H0 L0 MSN LSN 1409 F32.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble Figure 12:Set Burst Length Sequence Read Burst To execute a Read Burst operation the host drives CE# low, then sends the Read Burst command cycle (0CH), followed by three address cycles, and then one dummy cycle. Each cycle is two nibbles (clocks) long, most significant nibble first. After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. During Read Burst, the internal address pointer automatically increments until the last byte of the burst is reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the burst length, see Table 5. For example, if the burst length is eight Bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern would repeat until the command was terminated by a low-to-high transition on CE#. During this operation, blocks that are Read-locked will output data 00H. Table 5: Burst Address Ranges Burst Length 8 Bytes 16 Bytes 32 Bytes 64 Bytes Burst Address Ranges 00-07H, 08-0FH, 10-17H, 18-1FH... 00-0FH, 10-1FH, 20-2FH, 30-3FH... 00-1FH, 20-3FH, 40-5FH, 60-7FH... 00-3FH, 40-7FH, 80-BFH, C0-FFH T5.0 1409 (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 16 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information JEDEC-ID Read (SPI Protocol) Using traditional SPI protocol, the JEDEC-ID Read instruction identifies the device as SST26WF032 and the manufacturer as SST. To execute a JECEC-ID operation the host drives CE# low then sends the JEDEC-ID command cycle (9FH). For SPI modes, each cycle is eight bits (clocks) long, most significant bit first. Immediately following the command cycle the device outputs data on the falling edge of the SCK signal. The data output stream is continuous until terminated by a low-to-high transition on CE#. The device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure 13 for instruction sequence. Table 6: Device ID Data Output Device ID Product SST26WF032 Manufacturer ID (Byte 1) BFH Device Type (Byte 2) 26H Device ID (Byte 3) 22H T6.1 1409 CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SCK MODE 0 SI HIGH IMPEDANCE 9F SO BF MSB MSB 26 Device ID 1409 F38.0 Note: SIO2 and SIO3 must be driven VIH Figure 13:JEDEC-ID Sequence (SPI Mode) Quad J-ID Read (SQI Protocol) The Quad J-ID Read instruction identifies the device as SST26WF032 and manufacturer as SST. To execute a Quad J-ID operation the host drives CE# low and then sends the Quad J-ID command cycle (AFH). Each cycle is two nibbles (clocks) long, most significant nibble first. Immediately following the command cycle the device outputs data on the falling edge of the SCK signal. The data output stream is continuous until terminated by a low-to-high transition of CE#. The device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure 14 for instruction sequence. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 17 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information CE# MODE 3 0 2 4 6 8 10 12 N SCK SIO(3:0) MODE 0 C1 C0 H0 L0 H1 L1 H2 L2 H0 L0 H1 L4 H2 L2 MSN LSN BFH 26H Device ID BFH 26H Device ID HN LN N 1409 F39.0 Note: MSN = Most significant Nibble; LSN= Least Significant Nibble C[1:0]=AFH Figure 14:Quad J-ID Read Sequence Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to `1,' but it does not change a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. To execute a Sector-Erase operation, the host drives CE# low, then sends the Sector Erase command cycle (20H) and three address cycles, and then drives CE# high. Each cycle is two nibbles, or clocks, long, most significant nibble first. Address bits [AMS:A12] (AMS = Most Significant Address) determine the sector address (SAX); the remaining address bits can be VIL or VIH. Poll the BUSY bit in the Status register or wait TSE for the completion of the internal, self-timed, Sector-Erase operation. See Figure 15 for the Sector-Erase sequence. CE# MODE 3 0 1 2 4 6 SCK SIO(3:0) MODE 0 C1 C0 A5 A4 A3 A2 A1 A0 MSN LSN 1409 F07.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble C[1:0] = 20H Figure 15:4 KByte Sector-Erase Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 18 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Block-Erase The Block-Erase instruction clears all bits in the selected block to `1'. Block sizes can be 8 KByte, 32 KByte or 64 KByte depending on address, see Figure 3, Memory Map, for details. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any write operation, execute the WREN instruction. Keep CE# active low for the duration of any command sequence. To execute a Block-Erase operation, the host drives CE# low then sends the Block-Erase command cycle (D8H), three address cycles, then drives CE# high. Each cycle is two nibbles, or clocks, long, most significant nibble first. Address bits AMS-A13 determine the block address; the remaining address bits can be VIL or VIH. For 32 KByte blocks, A14:A13 can be VIL or VIH; for 64 KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY bit in the Status register or wait TBE for the completion of the internal, selftimed, Block-Erase operation See Figure 16 for the Block-Erase sequence. CE# MODE 3 0 1 2 4 6 SCK SIO(3:0) MODE 0 C1 C0 A5 A4 A3 A2 A1 A0 MSN LSN 1409 F08.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble C[1:0] = D8H Figure 16:Block-Erase Sequence Chip-Erase The Chip-Erase instruction clears all bits in the device to `1.' The Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any write operation, execute the the WREN instruction. To execute a Chip-Erase operation, the host drives CE# low, sends the Chip-Erase command cycle (C7H), then drives CE# high. A cycle is two nibbles, or clocks, long, most significant nibble first. Poll the BUSY bit in the Status register or wait TCE for the completion of the internal, self-timed, Chip-Erase operation. See Figure 17 for the Chip Erase sequence. CE# MODE 3 0 1 SCK SIO(3:0) MODE 0 C1 C0 1409 F09.0 Note: C[1:0] = C7H Figure 17:Chip-Erase Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 19 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Page-Program The Page-Program instruction programs up to 256 Bytes of data in the memory. The data for the selected page address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Program applied to a protected memory area will be ignored. Prior to the program operation, execute the WREN instruction. To execute a Page-Program operation, the host drives CE# low then sends the Page Program command cycle (02H), three address cycles followed by the data to be programmed, then drives CE# high. The programmed data must be between 1 to 256 Bytes and in whole Byte increments; sending an odd number of nibbles will cause the last nibble to be ignored. Each cycle is two nibbles (clocks) long, most significant bit first. Poll the BUSY bit in the Status register or wait TPP for the completion of the internal, self-timed, Page-Program operation. See Figure 18 for the Page-Program sequence. When executing Page-Program, the memory range for the SST26WF032 is divided into 256 Byte page boundaries. The device handles shifting of more than 256 Bytes of data by maintaining the last 256 Bytes of data as the correct data to be programmed. If the target address for the Page-Program instruction is not the beginning of the page boundary (A7:A0 are not all zero), and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. CE# MODE 3 0 2 4 6 8 10 12 542 SCK SIO(3:0) MODE 0 C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 MSN LSN Data Byte 0 Data Byte 1 Data Byte 2 HN LN Data Byte 255 1409 F10.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble C[1:0] = 02H Figure 18:Page-Program Sequence Write-Suspend and Write-Resume Write-Suspend allows the interruption of Sector-Erase, Block-Erase or Page-Program operations in order to erase, program, or read data in another portion of memory. The original operation can be continued with the Write-Resume command. Only one write operation can be suspended at a time; if an operation is already suspended, the device will ignore the Write-Suspend command. Write-Suspend during Chip-Erase is ignored; Chip-Erase is not a valid command while a write is suspended. Write-Suspend During Sector-Erase or Block-Erase Issuing a Write-Suspend instruction during Sector-Erase or Block-Erase allows the host to program or read any sector that was not being erased. The device will ignore any programming commands pointing to the suspended sector(s). Any attempt to read from the suspended sector(s) will output unknown data because the Sector- or Block-Erase will be incomplete. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 20 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information To execute a Write-Suspend operation, the host drives CE# low, sends the Write Suspend command cycle (B0H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. The Status register indicates that the erase has been suspended by changing the WSE bit from `0' to `1,' but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the BUSY bit in the Status register or wait TWS. Write Suspend During Page Programming Issuing a Write-Suspend instruction during Page Programming allows the host to erase or read any sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be ignored. Any attempt to read from the suspended page will output unknown data because the program will be incomplete. To execute a Write Suspend operation, the host drives CE# low, sends the Write Suspend command cycle (B0H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. The Status register indicates that the programming has been suspended by changing the WSP bit from `0' to `1,' but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the BUSY bit in the Status register or wait TWS. Write-Resume Write-Resume restarts a Write command that was suspended, and changes the suspend status bit in the Status register (WSE or WSP) back to `0'. To execute a Write-Resume operation, the host drives CE# low, sends the Write Resume command cycle (30H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed Write operation completed, poll the BUSY bit in the Status register, or wait the specified time TSE, TBE or TPP for Sector-Erase, Block-Erase, or Page-Programming, respectively. The total write time before suspend and after resume will not exceed the uninterrupted write times TSE, TBE or TPP. Read Security ID To execute a Read Security ID (SID) operation, the host drives CE# low, sends the Read Security ID command cycle (88H), one address cycle, and then two dummy cycles. Each cycle is two nibbles long, most significant nibble first. After the dummy cycles, the device outputs data on the falling edge of the SCK signal, starting from the specified address location. The data output stream is continuous through all SID addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until the last SID address is reached, then outputs 00H until CE# goes high. CE# MODE 3 0 1 2 7 8 9 10 11 12 13 SCK MODE 0 MSN LSN SIO[3:0] C0 C1 A1 A0 X X X X H0 L0 H1 L1 H2 L2 Command Address Dummy Data Byte 0 Data Byte 1 Data Byte 2 1409 F45.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble Figure 19:Read SID Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 21 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Program Security ID The Program Security ID instruction programs one to 24 Bytes of data in the user-programmable, Security ID space. The device ignores a Program Security ID instruction pointing to an invalid or protected address, see Table 7. Prior to the program operation, execute WREN. To execute a Program SID operation, the host drives CE# low, sends the Program Security ID command cycle (A5H), one address cycle, the data to be programmed, then drives CE# high. The programmed data must be between 1 to 24 Bytes and in whole Byte increments; sending an odd number of nibbles will cause the last nibble to be ignored. Each cycle is two nibbles long, most significant nibble first. To determine the completion of the internal, self-timed Program SID operation, poll the BUSY bit in the software status register, or wait TPSID for the completion of the internal self-timed Program Security ID operation. Table 7: Program Security ID Program Security ID Pre-Programmed at factory User Programmable Address Range 00H - 07H 08H - 1FH T7.0 1409 Lockout Security ID The Lockout Security ID instruction prevents any future changes to the Security ID. To execute a Lockout SID, the host drives CE# low, sends the Lockout Security ID command cycle (85H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. The user map polls the BUSY bit in the software status register or waits TPSID for the completion of he Lockout Security ID operation. Read-Status Register (RDSR) The Read-Status register (RDSR) command outputs the contents of the Status register. The Status register may be read at any time even during a Write operation. When a Write is in progress, check the BUSY bit before sending any new commands to assure that the new commands are properly received by the device. To execute a Read-Status-Register operation the host drives CE# low, then sends the Read-StatusRegister command cycle (05H). Each cycle is two nibbles long, most significant nibble first. Immediately after the command cycle, the device outputs data on the falling edge of the SCK signal. The data output stream continues until terminated by a low-to-high transition on CE#. See Figure 20 for the RDSR instruction sequence. CE# MODE 3 0 2 4 6 8 N SCK MODE 0 SIO(3:0) C1 C0 H0 L0 H0 L0 H0 L0 MSN LSN Status Byte Status Byte Status Byte Status Byte 1409 F11.0 H0 L0 Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble C[1:0] = 05H Figure 20:Read-Status-Register (RDSR) Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 22 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Write-Enable (WREN) The Write Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to `1,' allowing Write operations to occur. The WREN instruction must be executed prior to any of the following operations: Sector Erase, Block Erase, Chip Erase, Page Program, Program Security ID, Lockout Security ID, Write Block-Protection Register and Lockdown Block-Protection Register. To execute a Write Enable the host drives CE# low then sends the Write Enable command cycle (06H) then drives CE# high. A cycle is two nibbles (clocks) long, most significant nibble first. See Figure 21 for the WREN instruction sequence. CE# MODE 3 0 1 SCK SIO(3:0) MODE 0 C1 C0 1409 F12.0 Note: C[1:0] = 06H Figure 21:Write-Enable Sequence Write-Disable (WRDI) The Write-Disable (WRDI) instruction sets the Write-Enable-Latch bit in the Status Register to `0,' preventing Write execution without a prior WREN instruction. To execute a Write-Disable, the host drives CE# low, sends the Write Disable command cycle (04H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. CE# MODE 3 0 1 SCK SIO(3:0) MODE 0 C1 C0 1409 F33.0 Note: C[1:0] = 04H Figure 22:Write-Disable (WRDI) Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 23 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Read Block-Protection Register (RBPR) The Read Block-Protection Register instruction outputs the Block-Protection Register data which determines the protection status. To execute a Read Block-Protection Register operation, the host drives CE# low, and then sends the Read Block-Protection Register command cycle (72H). Each cycle is two nibbles long, most significant nibble first. After the command cycle, the device outputs data on the falling edge of the SCK signal starting with the most significant nibble, see Table 8 for definitions of each bit in the Block-Protection Register. The RBPR command does not wrap around. After all data has been output, the device will output 0H until terminated by a low-to-high transition on CE#. See Figure 23. CE# MODE 3 0 2 4 6 8 10 12 N SCK SIO(3:0) C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 MSN LSN BPR [m:m-7] HN L BPR [7:0] 1409 F34.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble Block Protection Register (BPR) m = 79 for SST26WF032 C[1:0]=72H Figure 23:Read Block Protection Register Sequence Write Block-Protection Register (WBPR) To execute a Write Block-Protection Register operation the host drives CE# low, sends the Write Block-Protection Register command cycle (42H), sends 10 cycles of data, and finally drives CE# high. Each cycle is two nibbles long, most significant nibble first. See Table 8 for definitions of each bit in the Block-Protection Register. CE# MODE 3 0 2 4 6 8 10 12 N SCK SIO(3:0) MODE 0 C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 MSN LSN BPR [m:m-7] HN LN BPR [7:0] 1409 F35.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble Block Protection Register (BPR) m = 79 for SST26WF032 C[1:0]=42H Figure 24:Write Block Protection Register Sequence (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 24 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Table 8: Block-Protection Register for 26WF032 (1 of 2)1 BPR Bits Read Lock 79 77 75 73 71 69 67 65 Write Lock 78 76 74 72 70 68 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address Range 3FE000H - 3FFFFFH 3FC000H - 3FDFFFH 3FA000H - 3FBFFFH 3F8000H - 3F9FFFH 006000H - 007FFFH 004000H - 005FFFH 002000H - 003FFFH 000000H - 001FFFH 3F0000H - 3F7FFFH 008000H - 00FFFFH 3E0000H - 3EFFFFH 3D0000H - 3DFFFFH 3C0000H - 3CFFFFH 3B0000H - 3BFFFFH 3A0000H - 3AFFFFH 390000H - 39FFFFH 380000H - 38FFFFH 370000H - 37FFFFH 360000H - 36FFFFH 350000H - 35FFFFH 340000H - 34FFFFH 330000H - 33FFFFH 320000H - 32FFFFH 310000H - 31FFFFH 300000H - 30FFFFH 2F0000H - 2FFFFFH 2E0000H - 2EFFFFH 2D0000H - 2DFFFFH 2C0000H - 2CFFFFH 2B0000H - 2BFFFFH 2A0000H - 2AFFFFH 290000H - 29FFFFH 280000H - 28FFFFH 270000H - 27FFFFH 260000H - 26FFFFH 250000H - 25FFFFH 240000H - 24FFFFH 230000H - 23FFFFH 220000H - 22FFFFH 210000H - 21FFFFH Protected Block Size 8 KByte 8 KByte 8 KByte 8 KByte 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte 32 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 25 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Table 8: Block-Protection Register for 26WF032 (Continued) (2 of 2)1 BPR Bits Read Lock Write Lock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Range 200000H - 20FFFFH 1F0000H - 1FFFFFH 1E0000H - 1EFFFFH 1D0000H - 1DFFFFH 1C0000H - 1CFFFFH 1B0000H - 1BFFFFH 1A0000H - 1AFFFFH 190000H - 19FFFFH 180000H - 18FFFFH 170000H - 17FFFFH 160000H - 16FFFFH 150000H - 15FFFFH 140000H - 14FFFFH 130000H - 13FFFFH 120000H - 12FFFFH 110000H - 11FFFFH 100000H - 10FFFFH 0F0000H - 0FFFFFH 0E0000H - 0EFFFFH 0D0000H - 0DFFFFH 0C0000H - 0CFFFFH 0B0000H - 0BFFFFH 0A0000H - 0AFFFFH 090000H - 09FFFFH 080000H - 08FFFFH 070000H - 07FFFFH 060000H - 06FFFFH 050000H - 05FFFFH 040000H - 04FFFFH 030000H - 03FFFFH 020000H - 02FFFFH 010000H - 01FFFFH Protected Block Size 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte 64 KByte T8.0 1409 1. All blocks are write-locked and read-unlocked after power-up or reset. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 26 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Lockdown Block-Protection Register (LBPR) The Lockdown Block-Protection Register instruction prevents changes to the Block-Protection Register. Lockdown resets after power cycling; this allows the Block-Protection Register to be changed. To execute a Lockdown Block-Protection Register, the host drives CE# low, then sends the Lockdown Block-Protection Register command cycle (8DH), then drives CE# high. A cycle is two nibbles long, most significant nibble first. CE# MODE 3 0 1 SCK SIO(3:0) MODE 0 C1 C0 1409 F30.0 Note: C[1:0]=8DH Figure 25:Lockdown Block-Protection Register (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 27 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. Table 9: Operating Range Range Industrial Ambient Temp -40C to +85C VDD 1.65-1.95V Table 10: AC Conditions of Test1 Input Rise/Fall Time 3ns 1. See Figure 29 Output Load CL = 30 pF T10.1 1409 (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 28 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 1.65V in less than 270 ms). See Table 11 and Figure 26 for more information. Table 11: Recommended System Power-up Timings Symbol TPU-READ1 TPU-WRITE 1 Parameter VDD Min to Read Operation VDD Min to Write Operation Minimum 100 100 Units s s T11.0 1409 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VDD VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. VDD Min TPU-READ TPU-WRITE Device fully accessible Time 1409 F27.0 Figure 26:Power-up Timing Diagram (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 29 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information DC Characteristics Table 12: DC Operating Characteristics (VDD = 1.65 - 1.95V) Limits Symbol Parameter IDDR Read Current Min Typ 12 Max 18 Units mA Test Conditions VDD=VDD Min, CE#=0.1 VDD/0.9 VDD@80 MHz, SO=open CE#=VDD CE#=VDD, VIN=VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min T12.0 1409 IDDW ISB1 ILI ILO VIL VIH VOL VOH Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD 8 30 25 1 1 0.3 0.2 mA A A A V V V V Table 13: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter COUT1 CIN 1 Description Output Pin Capacitance Input Capacitance Test Condition VOUT = 0V VIN = 0V Maximum 12 pF 6 pF T13.0 1409 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 14: Reliability Characteristics Symbol NEND1 TDR 1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T14.0 1409 ILTH1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 30 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information AC Characteristics Table 15: AC Operating Characteristics Limits - 25 MHz Symbol FCLK TCLK TSCKH TSCKL TSCKR1 TSCKF1 TCES2 TCEH 2 Limits - 80 MHz Min Max 80 12.5 5.5 5.5 0.1 0.1 6 5 3 3 12.5 Units MHz ns ns ns V/ns V/ns ns ns ns ns ns 12.5 0 4 4 0 ns ns ns ns ns 6 25 25 50 1.5 0.2 10 ns ms ms ms ms ms s T15.1 1409 Parameter Serial Clock Frequency Serial Clock Period Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time (slew rate) Serial Clock Fall Time (slew rate) CE# Active Setup Time CE# Active Hold Time CE# Not Active Setup Time CE# Not Active Hold Time CE# High Time CE# High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time Output Hold from SCK Change Output Valid from SCK Sector-Erase Block-Erase Chip-Erase Page-Program Program Security ID Write-Suspend Latency Min Max 25 40 18 18 0.1 0.1 12 12 10 10 100 15 0 5 5 0 15 25 25 50 1.5 0.2 10 TCHS2 TCHH TCPH TCHZ TCLZ TDS TDH TOH TV TSE TBE TSCE TPP TPSID TWS 2 1. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements 2. Relative to SCK. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 31 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information TCPH CE# TCHH SCK TDS TDH TSCKR TSCKF TCES TCEH TCHS SIO MSB LSB 1409 F24.0 Figure 27:Serial Input Timing Diagram CE# TSCKH SCK TCLZ SIO TV TOH MSB LSB 1409 F25.0 TSCKL TCHZ Figure 28:Serial Output Timing Diagram Table 16: Reset Timing Parameters TR(i) TR(o) TR(p) TR(e) Parameter Reset to Read (non-data operation) Reset Recovery from Program or Suspend Reset Recovery from Erase Minimum Maximum 10 100 1 Units ns s ms T16.0 1409 (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 32 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information TCPH CE# MODE 3 MODE 3 MODE 3 CLK MODE 0 MODE 0 MODE 0 SIO(3:0) C1 C0 C3 C2 1409 F14.0 Note: C[1:0] = 55H; C[3:2] = AAH Figure 29:Reset Timing Diagram VIHT VHT INPUT REFERENCE POINTS VHT OUTPUT VLT VILT VLT 1409 F28.0 AC test inputs are driven at VIHT (0.9VDD) for a logic `1' and VILT (0.1VDD) for a logic `0'. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%) are <3 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test Figure 30:AC Input/Output Reference Waveforms (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 33 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Product Ordering Information SST 26 XX WF XX 032 XXX 80 XX 4I XX - S2AE XXXX Environmental Attribute E1 = non-Pb / non-Sn contact (lead) finish Package Modifier A = 8 leads or contacts Package Type Q = WSON (6 mm x 5 mm) S2 = SOIC (200 mil body width) Temperature Range I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Operating Frequency 80 = 80 MHz Device Density 032 = 32 Mbit Voltage W = 1.65-1.95V Product Series 26 = Serial Quad I/O (SQI) Flash Memory 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST26WF032 SST26WF032-80-4I-QAE SST26WF032-80-4I-S2AE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 34 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Packaging Diagrams TOP VIEW Pin #1 Corner SIDE VIEW 0.2 BOTTOM VIEW Pin #1 1.27 BSC 5.00 0.10 0.076 4.0 3.4 0.48 0.35 6.00 0.10 0.80 0.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain VSS leads. This paddle can be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. 0.05 Max 0.70 0.50 CROSS SECTION 0.80 0.70 1mm 8-wson-5x6-QA-9.0 Figure 31:8-Contact Very-very-thin, Small-outline, No-lead (WSON) SST Package Code: QA (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 35 1.8V Serial Quad I/O (SQI) Flash Memory SST26WF032 Advance Information Pin #1 Identifier TOP VIEW SIDE VIEW 5.40 5.15 1.27 BSC 0.50 0.35 5.40 5.15 8.10 7.70 2.16 1.75 0.25 0.19 0.25 0.05 END VIEW 0 8 08-soic-EIAJ-S2A-3 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0.1 mm 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. 0.80 0.50 1mm Figure 32:8-Lead, Small Outline Integrated Circuit (SOIC) SST Package Code: S2A Table 17: Revision History Number 00 01 Description Date Nov 2009 Jan 2010 * * Initial release of data sheet Updated Table 12 on page 30 and Table 15 on page 31 (c) 2010 Silicon Storage Technology, Inc. All rights reserved. SST and the SST logo are registered trademarks of Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. Specifications are subject to change without notice. Refer to www.sst.com for the most recent data sheet versions. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale which are available on www.sst.com. Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2010 Silicon Storage Technology, Inc. S71409-01-000 01/10 36 |
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